RTL description concept

RTL description concept

I have a doubt about the concept of the RTL description within a VHDL design.

*Is the RTL a way of VHDL coding or an squematic design?

*If it´s VHDL coding, what are the differences with the "standar" VHDL code, because I´ve searched in many tutorials and it talks about concurrents(when..else) and secuencial (process) ejecutions, but they don´t talk about the RTL coding.

On the web I´ve found some tools to check, and verify the RTL(VHDL) design, so I would like to understand the RTL concept in order to understand how can I use those tools to improve the designs.

Many Thanks