Quantities und ihre Folgen...

Quantities und ihre Folgen...

Hi zusammen,

habe folgenden VHDL Code in einer Testbench:

library ieee;
use ieee.math_real.all;
use ieee.electrical_systems.all;


entity tb_aplf_passive is

end entity tb_aplf_passive;


architecture tb_aplf_passive_ams of tb_aplf_passive is

-- port map of aplf-sys-ea.vhd
terminal VCI : electrical;
terminal VCO : electrical;
terminal VSSA : electrical;

-- generating transient input-currents
quantity q_V_VCI across q_I_VCI through VCI;

-- input frequency
signal tran_freq:real:=0.0;

-- input amplitude
quantity tran_mag:real:=1.0;

-- circuit-frequency of input-voltage
quantity tran_w: real:=0.0;

-- generating ac input-currents
-- quantity tran_phase:real:=1.0e-12;

-- tran_phase from degree to circuit-value
-- constant phase: real:= tran_phase * math_deg_to_rad;


begin

-- acquirement circuit-frequency
process is
begin
tran_freq