create a shortened Clock Signal

create a shortened Clock Signal

Hello,

i am pretty new to vhdl so i might need some help.

I have a clock with about 2MHz called phi2.
This clock needs to be shortend in the high-phase.
The Altera FPGA has a 50MHz clock

I would write it in C like this:

If rising edge(clk50)
if rising edge (phi2)
phi2short = '1'
counter = 0
endif
if counter >= 9 // 180ns
phi2short = '0'
else
counter = counter +1
endif
endif

how would it be right as a vhdl ?

Wolfram.