ichbins
timein : in std_logic_vector(5 downto 0); -- im Port-Body
signal y2: integer range 0 to 63; -- vor Beginn des Codes innerhalb der architecture
y2
timein : in std_logic_vector(5 downto 0); -- im Port-Body
signal y2: integer range 0 to 63; -- vor Beginn des Codes innerhalb der architecture
y2
Lt. Google ...
The function provided by the std_logic_arith library can't convert a std_logic_vector to an integer because it is impossible to determine if it represents an unsigned or signed value. Functions that do this are included in the std_logic_unsigned and std_logic_signed libraries.
D.h. musst du anderst schreiben. Vielleicht hilft das ja weiter.