Can anyone tell why this kind of 12-bit pipo register won't synthetize in ModelSim:
library ieee; use ieee.std_logic_1164.all;
entity reg_12 is port( input: in std_logic_vector( 11 downto 0); sys_clk, reset, sample_rate: in std_logic; output: out std_logic_vector( 11 downto 0)); end reg_12;
architecture RTL of reg_12 is
begin
p0: process(sys_clk, reset, sample_rate)
variable reg: std_logic_vector( 11 downto 0);
begin if( reset = '1') then reg := ( others => '0'); elsif rising_edge( sys_clk) then if (sample_rate = '1') then reg := input; end if; end if;
output
Re: Register will not synthetize...
I think, you just have to use a shared variable, I am not sure, but I think so. Hope, you have luck... And you have to change the position of declaration of reg. Downwards, you can see it within the "=" lines
Zitat: Can anyone tell why this kind of 12-bit pipo register won't synthetize in ModelSim:
library ieee; use ieee.std_logic_1164.all;
entity reg_12 is port( input: in std_logic_vector( 11 downto 0); sys_clk, reset, sample_rate: in std_logic; output: out std_logic_vector( 11 downto 0)); end reg_12;
architecture RTL of reg_12 is ============================================== shared variable reg: std_logic_vector( 11 downto 0); ============================================== begin
p0: process(sys_clk, reset, sample_rate)
begin if( reset = '1') then reg := ( others => '0'); elsif rising_edge( sys_clk) then if (sample_rate = '1') then reg := input; end if; end if;