VHDL execution error

VHDL execution error

Hi all!!

We're having some problems with a finite-state machine in VHDL. When a button is pressed, it is supposed to go to its corresponding state, but the only thing we obtain in the simulation is that, if we press the BTN1 button, we go to the "0001" state, all right, but after that, if we press any other button, although button BTN1 is not pressed, the state machine goes to the "0001" state, ergo, the state of the BTN1 button. Here you have the source of the state machine:

architecture Behavioral of Maquina_Estados is
signal E: STD_LOGIC_VECTOR (3 downto 0):="0000";
signal ascii_cod: STD_LOGIC_VECTOR (7 downto 0);
begin
U: PROCESS (CLK, RST, BTN1, BTN2, BTN3, BTN4, BTN5, BTN6, BTN7)
BEGIN
IF (RST='1') then E if (BTN7='1') then E