VHDL-syntax error

Hello. Can any one tell me please, why i can use case operator only inside process.
The second question - why i can't realize this code. And which right code may substitute it?

process(op)
begin
case op is
when "00" =>
addition: c_l_addr port map (op1=>X,op2=>Y,c_in=>'0',c_out=>c_sum_out,sum=>sum_out));
when "01" =>
substract: substractor port map (c_in=>'0',c_out=>c_sub_out,op1=>X,op2=>Y,dif_sign=>c_sub_sign,dif=>sub_out);
when "10" =>
multiplier: carry_save_mult port map(X=>X,Y=>Y,P=>mul_out);
when "11" =>
divider: divider port map (X=>X,Y=>Y,Q=>div_q_out,R=>div_r_out);
end case;

(Of course i discribed all component above.)oject/3
it gives me next error.

ERROR:HDLParsers:164 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 402. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
WARNING:HDLParsers:901 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 402. Label addition is ignored.
ERROR:HDLParsers:164 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 404. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
WARNING:HDLParsers:901 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 404. Label substract is ignored.
ERROR:HDLParsers:164 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 406. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
WARNING:HDLParsers:901 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 406. Label multiplier is ignored.
ERROR:HDLParsers:164 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 408. parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
WARNING:HDLParsers:901 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 408. Label divider is ignored.
ERROR:HDLParsers:812 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 407. A value is missing in case.
ERROR:HDLParsers:164 - "D:/Nex_Xilinx_project/32_razryadnoe_ALU/32_razryadnoe_ALU.vhd" Line 410. parse error, unexpected SEMICOLON, expecting PROCESS

Re: VHDL-syntax error

Case inside process, not outside?
Hm, that's how it is defined in the VHDL syntax. Nothing you can change about. If you want to use as concurrent assignment you should use with .. select construct.

Your error messaged:
I believe it is not allowed to instantiate a component within such a construct, or within a process. Again, this is VHLD syntax definition. Details can surely be found in the LRM.

Re: VHDL-syntax error

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Re: VHDL-syntax error

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