VHDL-Forum - Syntax

Wertzuweisung std_logic_vector

Wertzuweisung std_logic_vector

Ich möchte einem Signal mit 32Bit Länge einen Wert zuweisen mithilfe einer anderen Variablen, die kürzer ist (z.B. 24Bit). siehe unten:

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SIGNAL signal1 : std_logic_vector(31 DOWNTO 0);
SIGNAL signal2 : std_logic_vector(23 DOWNTO 0);

signal1 wie kann ich also dem Signal "signal1" den Wert von "signal2" zuweisen? Bzw. wie kann ich aus "signal2" ein 32Bit-Vektor erzeugen, der den selben Wert besitzt?

Re: Wertzuweisung std_logic_vector

Hallo Lukas,

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SIGNAL signal1 : std_logic_vector(31 DOWNTO 0);
SIGNAL signal2 : std_logic_vector(23 DOWNTO 0);

signal1

Re: Wertzuweisung std_logic_vector

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Re: Wertzuweisung std_logic_vector

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Re: Wertzuweisung std_logic_vector

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